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Yixun Lan authored
According to the datasheet, the od shift of sys_pll is actually 16. Fixes: 78b4af31 ('clk: meson-axg: add clock controller drivers') Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> [fixed commit message] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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