• Thinh Nguyen's avatar
    usb: dwc3: Add DWC_usb31 GRXTHRCFG bit fields · 2fbc5bdc
    Thinh Nguyen authored
    Add new GRXTHRCFG bit field macros for DWC_usb31. The GRXTHRCFG register
    fields for DWC_usb31 is as follows:
     +-------+--------------------------+----------------------------------+
     | BITS  | Name                     | Description                      |
     +=======+==========================+==================================+
     | 31:27 | reserved                 |                                  |
     | 26    | UsbRxPktCntSel           | Async ESS receive packet         |
     |       |                          | threshold enable                 |
     | 25:21 | UsbRxPktCnt              | Async ESS receive packet         |
     |       |                          | threshold count                  |
     | 20:16 | UsbMaxRxBurstSize        | Async ESS Max receive burst size |
     | 15    | UsbRxThrNumPktSel_HS_Prd | HS high bandwidth periodic       |
     |       |                          | receive packet threshold enable  |
     | 14:13 | UsbRxThrNumPkt_HS_Prd    | HS high bandwidth periodic       |
     |       |                          | receive packet threshold count   |
     | 12:11 | reserved                 |                                  |
     | 10    | UsbRxThrNumPktSel_Prd    | Periodic ESS receive packet      |
     |       |                          | threshold enable                 |
     | 9:5   | UsbRxThrNumPkt_Prd       | Periodic ESS receive packet      |
     |       |                          | threshold count                  |
     | 4:0   | UsbMaxRxBurstSize_Prd    | Max periodic ESS RX burst size   |
     +-------+--------------------------+----------------------------------+
    Signed-off-by: default avatarThinh Nguyen <thinhn@synopsys.com>
    Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
    2fbc5bdc
core.h 43.4 KB