• Loic Poulain's avatar
    clk: qcom: Add CPU clock driver for msm8996 · 03e342dc
    Loic Poulain authored
    Each of the CPU clusters (Power and Perf) on msm8996 are
    clocked via 2 PLLs, a primary and alternate. There are also
    2 Mux'es, a primary and secondary all connected together
    as shown below
    
                                 +-------+
                  XO             |       |
              +------------------>0      |
                                 |       |
                       PLL/2     | SMUX  +----+
                         +------->1      |    |
                         |       |       |    |
                         |       +-------+    |    +-------+
                         |                    +---->0      |
                         |                         |       |
    +---------------+    |             +----------->1      | CPU clk
    |Primary PLL    +----+ PLL_EARLY   |           |       +------>
    |               +------+-----------+    +------>2 PMUX |
    +---------------+      |                |      |       |
                           |   +------+     |   +-->3      |
                           +--^+  ACD +-----+   |  +-------+
    +---------------+          +------+         |
    |Alt PLL        |                           |
    |               +---------------------------+
    +---------------+         PLL_EARLY
    
    The primary PLL is what drives the CPU clk, except for times
    when we are reprogramming the PLL itself (for rate changes) when
    we temporarily switch to an alternate PLL. A subsequent patch adds
    support to switch between primary and alternate PLL during rate
    changes.
    
    The primary PLL operates on a single VCO range, between 600MHz
    and 3GHz. However the CPUs do support OPPs with frequencies
    between 300MHz and 600MHz. In order to support running the CPUs
    at those frequencies we end up having to lock the PLL at twice
    the rate and drive the CPU clk via the PLL/2 output and SMUX.
    
    So for frequencies above 600MHz we follow the following path
     Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
    and for frequencies between 300MHz and 600MHz we follow
     Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
    
    ACD stands for Adaptive Clock Distribution and is used to
    detect voltage droops.
    Signed-off-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
    Rajendra Nayak: Initial RFC - https://lkml.org/lkml/2016/9/29/84Signed-off-by: default avatarIlia Lin <ilialin@codeaurora.org>
    Ilia Lin:  - reworked clock registering
               - Added clock-tree diagram
               - non-builtin support
               - clock notifier on rate change
               - https://lkml.org/lkml/2018/5/24/123Signed-off-by: default avatarLoic Poulain <loic.poulain@linaro.org>
    Loic Poulain: - fixed driver remove / clk deregistering
                  - Removed useless memory barriers
                  - devm usage when possible
                  - Fixed Kconfig depends
    
    Link: https://lore.kernel.org/r/1593766185-16346-3-git-send-email-loic.poulain@linaro.orgSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
    03e342dc
Kconfig 14.3 KB