Add support for Silvaco I3C dual-role IP. The master role is supported
in SDR mode only. I2C transfers have not been tested but are shared
because they are very close to the I3C transfers in terms of register
configuration.

The IBI processing follows this logic:
- When a slave advertizes an interrupt (SDA pulled low) an interrupt
  gets generated by the master. This time is unbounded and may be
  deferred.
- The IRQ handler itself does not process anything: it only queues a
  work that will be run in non-atomic context. This is needed because
  short wait periods must be experienced.
- The IBI job is divided in two parts: the first one is "critical" in
  the sense that it may not support getting interrupted. If this
  happens, after this first section the driver checks the master error
  register and depending on its content either flushes everything and
  errors out, or ends the processing (this second section may be
  interrupted).
- If the critical section got interrupted, the slave will
  automatically respin it's IBI request when it will be allowed to.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20210121101808.14654-6-miquel.raynal@bootlin.com