-
Guo Ren authored
CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine ISA Register misa. Every bit:1 indicate a feature, so we should beqz reset_done when there is no F/D bit in csr_misa register. Signed-off-by:
Guo Ren <ren_guo@c-sky.com> [paul.walmsley@sifive.com: fix typo in commit message] Fixes: 9e806356 ("riscv: clear the instruction cache and all registers when booting") Signed-off-by:
Paul Walmsley <paul.walmsley@sifive.com>
dc6fcba7