• Maxime Ripard's avatar
    clk: sunxi: mod0: Introduce MMC proper phase handling · 37e1041f
    Maxime Ripard authored
    The MMC clock we thought we had until now are actually not one but three
    different clocks.
    
    The main one is unchanged, and will have three outputs:
      - The clock fed into the MMC
      - a sample and output clocks, to deal with when should we output/sample data
        to/from the MMC bus
    
    The phase control we had are actually controlling the two latter clocks, but
    the main MMC one is unchanged.
    
    We can adjust the phase with a 3 bits value, from 0 to 7, 0 meaning a 180 phase
    shift, and the other values being the number of periods from the MMC parent
    clock to outphase the clock of.
    Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
    Acked-by: default avatarHans de Goede <hdegoede@redhat.com>
    37e1041f
clk-mod0.c 6.62 KB