• Stephen Boyd's avatar
    Merge branches 'clk-aspeed', 'clk-lock-UP', 'clk-mediatek' and 'clk-allwinner' into clk-next · c43a52cf
    Stephen Boyd authored
    * clk-aspeed:
      clk: aspeed: Handle inverse polarity of USB port 1 clock gate
      clk: aspeed: Fix return value check in aspeed_cc_init()
      clk: aspeed: Add reset controller
      clk: aspeed: Register gated clocks
      clk: aspeed: Add platform driver and register PLLs
      clk: aspeed: Register core clocks
      clk: Add clock driver for ASPEED BMC SoCs
      dt-bindings: clock: Add ASPEED constants
    
    * clk-lock-UP:
      clk: fix reentrancy of clk_enable() on UP systems
    
    * clk-mediatek:
      clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built
      clk: mediatek: Fix all warnings for missing struct clk_onecell_data
      clk: mediatek: fixup test-building of MediaTek clock drivers
      clk: mediatek: group drivers under indpendent menu
    
    * clk-allwinner:
      clk: sunxi-ng: a83t: Add M divider to TCON1 clock
      clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
      clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
      dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
      clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL
      clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL
      clk: sunxi-ng: Support fixed post-dividers on NM style clocks
      clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks
      clk: sunxi-ng: Support fixed post-dividers on MP style clocks
      clk: sunxi: Use PTR_ERR_OR_ZERO()
    c43a52cf
Makefile 3.9 KB