• Zhang Lei's avatar
    arm64: Add workaround for Fujitsu A64FX erratum 010001 · 3e32131a
    Zhang Lei authored
    On the Fujitsu-A64FX cores ver(1.0, 1.1), memory access may cause
    an undefined fault (Data abort, DFSC=0b111111). This fault occurs under
    a specific hardware condition when a load/store instruction performs an
    address translation. Any load/store instruction, except non-fault access
    including Armv8 and SVE might cause this undefined fault.
    
    The TCR_ELx.NFD1 bit is used by the kernel when CONFIG_RANDOMIZE_BASE
    is enabled to mitigate timing attacks against KASLR where the kernel
    address space could be probed using the FFR and suppressed fault on
    SVE loads.
    
    Since this erratum causes spurious exceptions, which may corrupt
    the exception registers, we clear the TCR_ELx.NFDx=1 bits when
    booting on an affected CPU.
    Signed-off-by: default avatarZhang Lei <zhang.lei@jp.fujitsu.com>
    [Generated MIDR value/mask for __cpu_setup(), removed spurious-fault handler
     and always disabled the NFDx bits on affected CPUs]
    Signed-off-by: default avatarJames Morse <james.morse@arm.com>
    Tested-by: default avatarzhang.lei <zhang.lei@jp.fujitsu.com>
    Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    3e32131a
assembler.h 17.7 KB