• Tudor Ambarus's avatar
    mtd: spi-nor: Rework the disabling of block write protection · 3e0930f1
    Tudor Ambarus authored
    spi_nor_unlock() unlocks blocks of memory or the entire flash memory
    array, if requested. clear_sr_bp() unlocks the entire flash memory
    array at boot time. This calls for some unification, clear_sr_bp() is
    just an optimization for the case when the unlock request covers the
    entire flash size.
    
    Get rid of clear_sr_bp() and introduce spi_nor_unlock_all(), which is
    just a call to spi_nor_unlock() for the entire flash memory array.
    This fixes a bug that was present in spi_nor_spansion_clear_sr_bp().
    When the QE bit was zero, we used the Write Status (01h) command with
    one data byte, which might cleared the Status Register 2. We now always
    use the Write Status (01h) command with two data bytes when
    SNOR_F_HAS_16BIT_SR is set, to avoid clearing the Status Register 2.
    
    The SNOR_F_NO_READ_CR case is treated as well. When the flash doesn't
    support the CR Read command, we make an assumption about the value of
    the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then
    spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can
    be sure the QE bit has value one, because of the previous call to
    spi_nor_quad_enable().
    
    Get rid of the MFR handling and implement specific manufacturer
    default_init() fixup hooks.
    
    Note that this changes a bit the logic for the SNOR_MFR_ATMEL,
    SNOR_MFR_INTEL and SNOR_MFR_SST cases. Before this patch, the Atmel,
    Intel and SST chips did not set the locking ops, but unlocked the entire
    flash at boot time, while now they are setting the locking ops to
    stm_locking_ops. This should work, since the disable of the block
    protection at the boot time used the same Status Register bits to unlock
    the flash, as in the stm_locking_ops case.
    Suggested-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
    Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
    Reviewed-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
    3e0930f1
spi-nor.c 153 KB