• Ira Weiny's avatar
    cxl/pci: Skip irq features if MSI/MSI-X are not supported · d72a4caf
    Ira Weiny authored
    CXL 3.1 Section 3.1.1 states:
    
    	"A Function on a CXL device must not generate INTx messages if
    	that Function participates in CXL.cache protocol or CXL.mem
    	protocols."
    
    The generic CXL memory driver only supports devices which use the
    CXL.mem protocol.  The current driver attempts to allocate MSI/MSI-X
    vectors in anticipation of their need for mailbox interrupts or event
    processing.  However, the above requirement does not require a device to
    support interrupts, only that they use MSI/MSI-X.  For example, a device
    may disable mailbox interrupts and either be configured for firmware
    first or skip event processing and function.
    
    Dave Larsen reported that the following Intel / Agilex card does not
    support interrupts on function 0.
    
    	CXL: Intel Corporation Device 0ddb (rev 01) (prog-if 10 [CXL Memory Device (CXL 2.x)])
    
    Rather than fail device probe if interrupts are not supported; flag that
    irqs are not enabled and avoid features which require interrupts.
    Emit messages appropriate for the situation to aid in debugging should
    device behavior be unexpected due to a failure to allocate vectors.
    
    Note that it is possible for a device to have host based event
    processing through polling.  However, the driver does not support
    polling and it is not anticipated to be generally required.  Leave that
    functionality to a future patch if such a device comes along.
    Reported-by: default avatarDave Larsen <davelarsen58@gmail.com>
    Reviewed-by: default avatarDave Jiang <dave.jiang@intel.com>
    Reviewed-by: default avatarFan Ni <fan.ni@samsung.com>
    Signed-off-by: default avatarIra Weiny <ira.weiny@intel.com>
    Reviewed-and-tested-by: default avatarDavidlohr Bueso <dave@stgolabs.net>
    Link: https://lore.kernel.org/r/20240117-dont-fail-irq-v2-1-f33f26b0e365@intel.comSigned-off-by: default avatarDan Williams <dan.j.williams@intel.com>
    d72a4caf
pci.c 28.3 KB