1. Xena3's with a set of subsystem IDs had Link LED problems, fixed
that specifically for them.

2. To write into the Keyed Mac_Cfg register to enable broadcast,
writing two 32 bit writes into it along with a write to the key
register rather than a single write to key and a 64 bit write to
mac_cfg. This is necessary on 32 bit systems where a writeq(64 bit
write) is actually two writel (32 bit writes).

3. Writes to some special registers mentioned in UG is being done by
a special macro which defines which 32 bits of the 64 bit register
is to be written first. Again this applies only on 32 bit systems.

4. Configured pause frame related water marks and a shared_split
value which describes the Max TXDMA related split transaction that
can be used without giving room for the Rx transactions.

5. The mac_rmac_err_reg R1 register will be cleared in  the interrupt
handler itself rather than in the scheduled task as was being done
previously.

6. Even on PCC_FB_ECC error the card will be reset by disabling
adapter enable bit.
Signed-off-by: Raghavendra Koushik <raghavendra.koushik@s2io.com>
Signed-off-by: Ravinandan Arakali <ravinandan.arakali@s2io.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>