We know where the PCIe capability lives in the host bridge's config space;
in fact, we already hard-coded the offset of the Link Control 2 register.

The hard-coded Link Control 2 offset was 0xdc.  Link Control 2 is at offset
0x30 into the PCIe capability, so the capability itself must be at
0xdc - 0x30 = 0xac.

Hard-code the PCIe capability offset, which means we don't have to search
for it and we can use the standard definitions for registers within the
capability.

No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>