• Paul Burton's avatar
    MIPS: Support for hybrid FPRs · 4227a2d4
    Paul Burton authored
    Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but
    accesses to odd indexed single registers use bits 63:32 of the
    preceeding even indexed 64b register. In this mode all FP code
    except that built for the plain FP64 ABI can execute correctly. Most
    notably a combination of FP64A & FP32 code can execute correctly,
    allowing for existing FP32 binaries to be linked with new FP64A binaries
    that can make use of 64 bit FP & MSA.
    
    Hybrid FPRs are implemented by setting both the FR & FRE bits, trapping
    & emulating single precision FP instructions (via Reserved Instruction
    exceptions) whilst allowing others to execute natively. It therefore has
    a penalty in terms of execution speed, and should only be used when no
    fully native mode can be. As more binaries are recompiled to use either
    the FPXX or FP64(A) ABIs, the need for hybrid FPRs should diminish.
    However in the short to mid term it allows for a gradual transition
    towards that world, rather than a complete ABI break which is not
    feasible for some users & not desirable for many.
    
    A task will be executed using the hybrid FPR scheme when its
    TIF_HYBRID_FPREGS flag is set & TIF_32BIT_FPREGS is clear. A further
    patch will set the flags as necessary, this patch simply adds the
    infrastructure necessary for the hybrid FPR mode to work.
    Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
    Cc: linux-mips@linux-mips.org
    Cc: Alexander Viro <viro@zeniv.linux.org.uk>
    Cc: linux-fsdevel@vger.kernel.org
    Cc: linux-kernel@vger.kernel.org
    Patchwork: https://patchwork.linux-mips.org/patch/7683/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    4227a2d4
traps.c 54.7 KB