Add support to read the optional "gate" clock property and request the
clock which will be used to ungate the DLL clock.

For Xilinx platforms which has DLL module, dll clock must be
ungated/enabled when SD controller operates at higher frequencies like 50
MHz, 100 MHz and 200 MHz. This will be done by explicitly requesting gate
clock from the driver.
Signed-off-by: Swati Agarwal <swati.agarwal@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20230223141402.23979-1-swati.agarwal@amd.comSigned-off-by: Ulf Hansson <ulf.hansson@linaro.org>