1. Set extended packet length bit in phy register 0x18 shadow register 0
on all chips that support jumbo frames (i.e. all chips except 5705 and
its variants). Jumbo frame reception is less reliable (more CRC errors)
if this bit is not set. This bit can be set regardless of the current
MTU setting.


2. Remove FTQ reset during chip init. This is the best fix for the ASF
race condition problem that I mentioned a few months ago. The FTQ reset
is redundant as it is already reset during GRC reset.