In a recent thread it was mentioned that some architectures, such as PPC,
do not guarantee relative ordering between different varieties of
processor/device data transfers.  This patch adds an mb() instruction to
the UHCI driver, to insure that the data structures in memory (cached by
the CPU and accessed by DMA) are fully flushed before the controller is
started (by regular bus IO).
Signed-off-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <greg@kroah.com>