Enable multi-master mode in I2C_CNFG reg based on hw features.
Using single/multi-master mode bit introduced for Tegra210,
whereas multi-master mode is enabled by default in HW for T124 and
earlier Tegra SOC. Enabling this bit doesn't explicitly start
treating the bus has having multiple masters, but will start
checking for arbitration lost and reporting when it occurs.

The Tegra210 I2C controller supports single/multi master mode.
Add chipdata for Tegra210 and its compatibility string so that
Tegra210 will select data that enables multi master mode correctly.

Do below prerequisites for multi-master bus if "multi-master"
dt property entry is added.
 1. Enable 1st level clock always set.
 2. Disable 2nd level clock gating (slcg which
    is supported from T124 SOC and later chips)
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>