• Shawn Guo's avatar
    ARM: imx: fix vf610 enet module clock selection · 4f71612e
    Shawn Guo authored
    The fec/enet driver calculates MDC rate with the formula below.
    
      ref_freq / ((MII_SPEED + 1) x 2)
    
    The ref_freq here is the fec internal module clock, which is missing
    from clk-vf610 clock driver right now.  And clk-vf610 driver mistakenly
    supplies RMII clock (50 MHz) as the source to fec.  This results in the
    situation that fec driver gets ref_freq as 50 MHz, while physically it
    runs at 66 MHz (fec module clock physically sources from ipg which runs
    at 66 MHz).  That's why software expects MDC runs at 2.5 MHz, while the
    measurement tells it runs at 3.3 MHz.  And this causes the PHY KSZ8041
    keeps swithing between Full and Half mode as below.
    
      libphy: 400d0000.etherne:00 - Link is Up - 100/Full
      libphy: 400d0000.etherne:00 - Link is Up - 100/Half
      libphy: 400d0000.etherne:00 - Link is Up - 100/Full
      libphy: 400d0000.etherne:00 - Link is Up - 100/Half
      libphy: 400d0000.etherne:00 - Link is Up - 100/Full
      libphy: 400d0000.etherne:00 - Link is Up - 100/Half
    
    Add the missing module clock for ENET0 and ENET1, and correct the clock
    supplying in device tree to fix above issue.
    
    Thanks to Alison Wang <b18965@freescale.com> for debugging the issue.
    Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
    4f71612e
clk-vf610.c 18.1 KB