• Ville Syrjälä's avatar
    drm/i915: Fix rawclk readout for g4x · 82f2b4ac
    Ville Syrjälä authored
    Turns out our skills in decoding the CLKCFG register weren't good
    enough. On this particular elk the answer we got was 400 MHz when
    in reality the clock was running at 266 MHz, which then caused us
    to program a bogus AUX clock divider that caused all AUX communication
    to fail.
    
    Sadly the docs are now in bit heaven, so the fix will have to be based
    on empirical evidence. Using another elk machine I was able to frob
    the FSB frequency from the BIOS and see how it affects the CLKCFG
    register. The machine seesm to use a frequency of 266 MHz by default,
    and fortunately it still boot even with the 50% CPU overclock that
    we get when we bump the FSB up to 400 MHz.
    
    It turns out the actual FSB frequency and the register have no real
    link whatsoever. The register value is based on some straps or something,
    but fortunately those too can be configured from the BIOS on this board,
    although it doesn't seem to respect the settings 100%. In the end I was
    able to derive the following relationship:
    
    BIOS FSB / strap | CLKCFG
    -------------------------
    200              | 0x2
    266              | 0x0
    333              | 0x4
    400              | 0x4
    
    So only the 200 and 400 MHz cases actually match how we're currently
    decoding that register. But as the comment next to some of the defines
    says, we have been just guessing anyway.
    
    So let's fix things up so that at least the 266 MHz case will work
    correctly as that is actually the setting used by both the buggy
    machine and my test machine.
    
    The fact that 333 and 400 MHz BIOS settings result in the same register
    value is a little disappointing, as that means we can't tell them apart.
    However, according to the gmch datasheet for both elk and ctg 400 Mhz is
    not even a supported FSB frequency, so I'm going to make the assumption
    that we should decode it as 333 MHz instead.
    
    Cc: stable@vger.kernel.org
    Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
    Reported-by: default avatarTomi Sarvela <tomi.p.sarvela@intel.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100926Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Link: http://patchwork.freedesktop.org/patch/msgid/20170504181530.6908-1-ville.syrjala@linux.intel.comAcked-by: default avatarJani Nikula <jani.nikula@intel.com>
    Tested-by: default avatarTomi Sarvela <tomi.p.sarvela@intel.com>
    (cherry picked from commit 6f38123e)
    Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
    82f2b4ac
i915_reg.h 345 KB