• Gautham R. Shenoy's avatar
    cpuidle: pseries: Fixup CEDE0 latency only for POWER10 onwards · 50741b70
    Gautham R. Shenoy authored
    Commit d947fb4c ("cpuidle: pseries: Fixup exit latency for
    CEDE(0)") sets the exit latency of CEDE(0) based on the latency values
    of the Extended CEDE states advertised by the platform
    
    On POWER9 LPARs, the firmwares advertise a very low value of 2us for
    CEDE1 exit latency on a Dedicated LPAR. The latency advertized by the
    PHYP hypervisor corresponds to the latency required to wakeup from the
    underlying hardware idle state. However the wakeup latency from the
    LPAR perspective should include
    
    1. The time taken to transition the CPU from the Hypervisor into the
       LPAR post wakeup from platform idle state
    
    2. Time taken to send the IPI from the source CPU (waker) to the idle
       target CPU (wakee).
    
    1. can be measured via timer idle test, where we queue a timer, say
    for 1ms, and enter the CEDE state. When the timer fires, in the timer
    handler we compute how much extra timer over the expected 1ms have we
    consumed. On a a POWER9 LPAR the numbers are
    
    CEDE latency measured using a timer (numbers in ns)
    N       Min      Median   Avg       90%ile  99%ile    Max    Stddev
    400     2601     5677     5668.74    5917    6413     9299   455.01
    
    1. and 2. combined can be determined by an IPI latency test where we
    send an IPI to an idle CPU and in the handler compute the time
    difference between when the IPI was sent and when the handler ran. We
    see the following numbers on POWER9 LPAR.
    
    CEDE latency measured using an IPI (numbers in ns)
    N       Min      Median   Avg       90%ile  99%ile    Max    Stddev
    400     711      7564     7369.43   8559    9514      9698   1200.01
    
    Suppose, we consider the 99th percentile latency value measured using
    the IPI to be the wakeup latency, the value would be 9.5us This is in
    the ballpark of the default value of 10us.
    
    Hence, use the exit latency of CEDE(0) based on the latency values
    advertized by platform only from POWER10 onwards. The values
    advertized on POWER10 platforms is more realistic and informed by the
    latency measurements. For earlier platforms stick to the default value
    of 10us. The fix was suggested by Michael Ellerman.
    
    Fixes: d947fb4c ("cpuidle: pseries: Fixup exit latency for CEDE(0)")
    Reported-by: default avatarEnrico Joedecke <joedecke@de.ibm.com>
    Signed-off-by: default avatarGautham R. Shenoy <ego@linux.vnet.ibm.com>
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    Link: https://lore.kernel.org/r/1626676399-15975-2-git-send-email-ego@linux.vnet.ibm.com
    50741b70
cpuidle-pseries.c 12.2 KB