• Andy Gospodarek's avatar
    bgmac: stop clearing DMA receive control register right after it is set · 50ef5ffe
    Andy Gospodarek authored
    commit fcdefcca upstream.
    
    Current bgmac code initializes some DMA settings in the receive control
    register for some hardware and then immediately clears those settings.
    Not clearing those settings results in ~420Mbps *improvement* in
    throughput; this system can now receive frames at line-rate on Broadcom
    5871x hardware compared to ~520Mbps today.  I also tested a few other
    values but found there to be no discernible difference in CPU
    utilization even if burst size and prefetching values are different.
    
    On the hardware tested there was no need to keep the code that cleared
    all but bits 16-17, but since there is a wide variety of hardware that
    used this driver (I did not look at all hardware docs for hardware using
    this IP block), I find it wise to move this call up and clear bits just
    after reading the default value from the hardware rather than completely
    removing it.
    
    This is a good candidate for -stable >=3.14 since that is when the code
    that was supposed to improve performance (but did not) was introduced.
    Signed-off-by: default avatarAndy Gospodarek <gospo@broadcom.com>
    Fixes: 56ceecde ("bgmac: initialize the DMA controller of core...")
    Cc: Hauke Mehrtens <hauke@hauke-m.de>
    Acked-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    [bwh: Backported to 3.16: adjust context]
    Signed-off-by: default avatarBen Hutchings <ben@decadent.org.uk>
    50ef5ffe
bgmac.c 42.4 KB