• Chris Metcalf's avatar
    arch/tile: use interrupt critical sections less · 51007004
    Chris Metcalf authored
    In general we want to avoid ever touching memory while within an
    interrupt critical section, since the page fault path goes through
    a different path from the hypervisor when in an interrupt critical
    section, and we carefully decided with tilegx that we didn't need
    to support this path in the kernel.  (On tilepro we did implement
    that path as part of supporting atomic instructions in software.)
    
    In practice we always need to touch the kernel stack, since that's
    where we store the interrupt state before releasing the critical
    section, but this change cleans up a few things.  The IRQ_ENABLE
    macro is split up so that when we want to enable interrupts in a
    deferred way (e.g. for cpu_idle or for interrupt return) we can
    read the per-cpu enable mask before entering the critical section.
    The cache-migration code is changed to use interrupt masking instead
    of interrupt critical sections.  And, the interrupt-entry code is
    changed so that we defer loading "tp" from per-cpu data until after
    we have released the interrupt critical section.
    Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
    51007004
migrate_64.S 3.5 KB