• José Roberto de Souza's avatar
    drm/i915/icl: Fix VEBOX mismatch BUG_ON() · 547fcf9b
    José Roberto de Souza authored
    GT VEBOX DISABLE is only 4 bits wide but it was using a 8 bits wide
    mask, the remaning reserved bits is set to 0 causing 4 more
    nonexistent VEBOX engines being detected as enabled, triggering the
    BUG_ON() because of mismatch between vebox_mask and newly added
    VEBOX_MASK().
    
    [   64.081621] [drm:intel_device_info_init_mmio [i915]] vdbox enable: 0005, instances: 0005
    [   64.081763] [drm:intel_device_info_init_mmio [i915]] vebox enable: 00f1, instances: 0001
    [   64.081825] intel_device_info_init_mmio:925 GEM_BUG_ON(vebox_mask != ({ unsigned int first__ = (VECS0); unsigned int count__ = (2); ((&(dev_priv)->__info)->engine_mask & (((~0UL) - (1UL << (first__)) + 1) & (~0UL >> (64 - 1 - (first__ + count__ - 1))))) >> first__; }))
    [   64.082047] ------------[ cut here ]------------
    [   64.082054] kernel BUG at drivers/gpu/drm/i915/intel_device_info.c:925!
    
    BSpec: 20680
    Fixes: 9511cb64 ("drm/i915: Adding missing '; ' to ENGINE_INSTANCES")
    Fixes: 26376a7e ("drm/i915/icl: Check for fused-off VDBOX and VEBOX instances")
    Cc: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
    Cc: Oscar Mateo <oscar.mateo@intel.com>
    Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
    Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Link: https://patchwork.freedesktop.org/patch/msgid/20190326230223.26336-1-jose.souza@intel.com
    547fcf9b
i915_reg.h 452 KB