• Maciej W. Rozycki's avatar
    MIPS: Fix MIPS I ISA /proc/cpuinfo reporting · e5f5a5b0
    Maciej W. Rozycki authored
    Correct a commit 515a6393 ("MIPS: kernel: proc: Add MIPS R6 support
    to /proc/cpuinfo") regression that caused MIPS I systems to show no ISA
    levels supported in /proc/cpuinfo, e.g.:
    
    system type		: Digital DECstation 2100/3100
    machine			: Unknown
    processor		: 0
    cpu model		: R3000 V2.0  FPU V2.0
    BogoMIPS		: 10.69
    wait instruction	: no
    microsecond timers	: no
    tlb_entries		: 64
    extra interrupt vector	: no
    hardware watchpoint	: no
    isa			:
    ASEs implemented	:
    shadow register sets	: 1
    kscratch registers	: 0
    package			: 0
    core			: 0
    VCED exceptions		: not available
    VCEI exceptions		: not available
    
    and similarly exclude `mips1' from the ISA list for any processors below
    MIPSr1.  This is because the condition to show `mips1' on has been made
    `cpu_has_mips_r1' rather than newly-introduced `cpu_has_mips_1'.  Use
    the correct condition then.
    
    Fixes: 515a6393 ("MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfo")
    Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
    Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
    Cc: linux-mips@linux-mips.org
    Cc: stable@vger.kernel.org # 3.19+
    Patchwork: https://patchwork.linux-mips.org/patch/16758/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    e5f5a5b0
proc.c 5.3 KB