• Rich Felker's avatar
    sh: disable aliased page logic on NOMMU models · 57155c65
    Rich Felker authored
    SH3/4 (with MMU) have a virtually indexed cache, requiring explicit
    work to avoid consistency problems arising from having the same
    physical address range cached in multiple cache lines. This is
    unneeded for the NOMMU case, and some of the resulting code paths
    (kmap_coherent) don't work. SH2 only avoided this problem by having a
    4-way associative cache with way size equal to the page size (4k),
    yielding no cache index bits outside of the page offset and thus no
    aliases.
    Signed-off-by: default avatarRich Felker <dalias@libc.org>
    57155c65
init.c 8.4 KB