• Matt Roper's avatar
    drm/i915/gen11: Allow usage of all GPIO pins · 5a6b7ef6
    Matt Roper authored
    Our pin mapping tables for ICP and MCC currently only list the standard
    GPIO pins used for various output ports.  Even through ICP's standard
    pin usage only utilizes pins 1, 2, and 9-12, and MCC's standard pin
    usage only uses pins 1, 2, and 9, these platforms do still have GPIO
    registers to address pins in the range 1-3 and 9-14.  OEM's may remap
    GPIO usage in non-standard ways (and provide the actual mapping via VBT
    settings), so we shouldn't exclude pins on these platforms just because
    they aren't part of the standard mappings.
    
    TGP's standard pin tables contains all the possible pins, so let's
    rename them to "icp" and use them for all PCH >= PCH_ICP.  This will
    prevent intel_gmbus_is_valid_pin from rejecting non-standard pin usage
    that an OEM specifies via the VBT.
    
    Note that this will cause pin 9 to be labeled as "tc1" instead of "dpc"
    in debug messages on platforms with the MCC PCH, but that may actually
    help avoid confusion since the text strings will now be the same on all
    gen11+ platforms instead of being different on just EHL.
    
    v2: Drop now-unused MCC_DDC_BUS_DDI_* names.
    
    v3: We want to compare against INTEL_PCH_TYPE, not INTEL_PCH_ID.
    
    Bspec: 8417
    Cc: José Roberto de Souza <jose.souza@intel.com>
    Cc: Lucas De Marchi <lucas.demarchi@intel.com>
    Cc: Vivek Kasireddy <vivek.kasireddy@intel.com>
    Cc: Jani Nikula <jani.nikula@intel.com>
    Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
    Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20190817005041.20651-1-matthew.d.roper@intel.com
    5a6b7ef6
intel_gmbus.c 24.4 KB