• Roland Stigge's avatar
    i2c: pnx: Fix read transactions of >= 2 bytes · c076ada4
    Roland Stigge authored
    On transactions with n>=2 bytes, the controller actually wrongly clocks in n+1
    bytes. This is caused by the (wrong) assumption that RFE in the Status Register
    is 1 iff there is no byte already ordered (via a dummy TX byte). This lead to
    the implementation of synchronized byte ordering, e.g.:
    
    Dummy-TX - RX - Dummy-TX - RX - ...
    
    But since RFE actually stays high after some Dummy-TX, it rather looks like:
    
    Dummy-TX - Dummy-TX - RX - Dummy-TX - RX - (RX)
    
    The last RX byte is clocked in by the bus controller, but ignored by the kernel
    when filling the userspace buffer.
    
    This patch fixes the issue by asking for RX via Dummy-TX asynchronously.
    Introducing a separate counter for TX bytes.
    Signed-off-by: default avatarRoland Stigge <stigge@antcom.de>
    Signed-off-by: default avatarWolfram Sang <w.sang@pengutronix.de>
    c076ada4
i2c-pnx.c 21.9 KB