• Lu Baolu's avatar
    iommu/vt-d: Add 256-bit invalidation descriptor support · 5d308fc1
    Lu Baolu authored
    Intel vt-d spec rev3.0 requires software to use 256-bit
    descriptors in invalidation queue. As the spec reads in
    section 6.5.2:
    
    Remapping hardware supporting Scalable Mode Translations
    (ECAP_REG.SMTS=1) allow software to additionally program
    the width of the descriptors (128-bits or 256-bits) that
    will be written into the Queue. Software should setup the
    Invalidation Queue for 256-bit descriptors before progra-
    mming remapping hardware for scalable-mode translation as
    128-bit descriptors are treated as invalid descriptors
    (see Table 21 in Section 6.5.2.10) in scalable-mode.
    
    This patch adds 256-bit invalidation descriptor support
    if the hardware presents scalable mode capability.
    
    Cc: Ashok Raj <ashok.raj@intel.com>
    Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
    Cc: Kevin Tian <kevin.tian@intel.com>
    Signed-off-by: default avatarSanjay Kumar <sanjay.k.kumar@intel.com>
    Signed-off-by: default avatarLiu Yi L <yi.l.liu@intel.com>
    Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
    Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
    5d308fc1
intel-svm.c 18.5 KB