• Chen-Yu Tsai's avatar
    clk: sunxi-ng: Add A80 Display Engine CCU · 783ab76a
    Chen-Yu Tsai authored
    With the A80 SoC, Allwinner grouped and moved some subsystem specific
    clock controls to a separate address space, and possibly separate
    hardware block.
    
    One such subsystem is the display engine. The main clock control unit
    now only has 1 set of bus gate, dram gate, module clock, and reset
    control for the entire display subsystem. These feed into a secondary
    clock control unit, which has controls for each individual module
    of the display pipeline. This block is not documented in the user
    manual. Allwinner's kernel was used as the reference.
    
    Add support for the display engine clock controls found on the A80.
    Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
    Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
    783ab76a
sun9i-a80-de.h 2.79 KB