• Daniel Thompson's avatar
    clk: stm32: Add clock driver for STM32F4[23]xxx devices · 358bdf89
    Daniel Thompson authored
    The driver supports decoding and statically modelling PLL state (i.e.
    we inherit state from bootloader) and provides support for all
    peripherals that support simple one-bit gated clocks. The covers all
    peripherals whose clocks come from the AHB, APB1 or APB2 buses.
    
    It has been tested on an STM32F429I-Discovery board. The clock counts
    for TIM2, USART1 and SYSTICK are all set correctly and the wall clock
    looks OK when checked with a stopwatch. I have also tested a prototype
    driver for the RNG hardware. The RNG clock is correctly enabled by the
    framework (also did inverse test and proved that by changing DT to
    configure the wrong clock bit then we observe the RNG driver to fail).
    Signed-off-by: default avatarDaniel Thompson <daniel.thompson@linaro.org>
    Reviewed-by: default avatarMaxime Coquelin <mcoquelin.stm32@gmail.com>
    [sboyd@codeaurora.org: Silence sparse warnings]
    Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
    358bdf89
clk-stm32f4.c 11.8 KB