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Mylène Josserand authored
The audio DAI needs to set the clock rates of the ac-dig clock. To make it possible, the parent PLL audio clock rates should also be changed. This is possible via "CLK_SET_RATE_PARENT" flag. Signed-off-by:
Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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