• Anup Patel's avatar
    RISC-V: Implement ASID allocator · 65d4b9c5
    Anup Patel authored
    Currently, we do local TLB flush on every MM switch. This is very harsh on
    performance because we are forcing page table walks after every MM switch.
    
    This patch implements ASID allocator for assigning an ASID to a MM context.
    The number of ASIDs are limited in HW so we create a logical entity named
    CONTEXTID for assigning to MM context. The lower bits of CONTEXTID are ASID
    and upper bits are VERSION number. The number of usable ASID bits supported
    by HW are detected at boot-time by writing 1s to ASID bits in SATP CSR.
    
    We allocate new CONTEXTID on first MM switch for a MM context where the
    ASID is allocated from an ASID bitmap and VERSION is provide by an atomic
    counter. At time of allocating new CONTEXTID, if we run out of available
    ASIDs then:
    1. We flush the ASID bitmap
    2. Increment current VERSION atomic counter
    3. Re-allocate ASID from ASID bitmap
    4. Flush TLB on all CPUs
    5. Try CONTEXTID re-assignment on all CPUs
    
    Please note that we don't use ASID #0 because it is used at boot-time by
    all CPUs for initial MM context. Also, newly created context is always
    assigned CONTEXTID #0 (i.e. VERSION #0 and ASID #0) which is an invalid
    context in our implementation.
    
    Using above approach, we have virtually infinite CONTEXTIDs on-top-of
    limited number of HW ASIDs. This approach is inspired from ASID allocator
    used for Linux ARM/ARM64 but we have adapted it for RISC-V. Overall, this
    ASID allocator helps us reduce rate of local TLB flushes on every CPU
    thereby increasing performance.
    
    This patch is tested on QEMU virt machine, Spike and SiFive Unleashed
    board. On QEMU virt machine, we see some (3-5% approx) performance
    improvement with SW emulated TLBs provided by QEMU. Unfortunately,
    the ASID bits of the SATP CSR are not implemented on Spike and SiFive
    Unleashed board so we don't see any change in performance. On real HW
    having all ASID bits implemented, the performance gains will be much
    more due improved sharing of TLB among different processes.
    Signed-off-by: default avatarAnup Patel <anup.patel@wdc.com>
    Reviewed-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
    Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
    65d4b9c5
context.c 8.98 KB