• Imre Deak's avatar
    drm/i915/icl: Add power well support · 67ca07e7
    Imre Deak authored
    Add the definition for ICL power wells and their mapping to power
    domains. On ICL there are 3 power well control registers, we'll select
    the correct one based on higher bits of the power well ID. The offset
    for the control and status flags within this register is based on the
    lower bits of the ID as on older platforms.
    
    As the DC state programming is also the same as on old platforms we can
    reuse the corresponding helpers. For this we mark here the DC-off power
    well as shared among multiple platforms.
    
    Other than the above the delta between old platforms and ICL:
    - Pipe C has its own power well, so we can save some additional power in the
      pipe A+B and (non-eDP) pipe A configurations.
    - Power wells for port E/F DDI/AUX IO and Thunderbolt 1-4 AUX IO
    
    v2:
    - Rebase on drm-tip after prep patch for this was merged there as
      requested by Paulo.
    - Actually add the new AUX and DDI power well control regs (Rakshmi)
    
    v3:
    - Fix power well register names in code comments
    - Add TBT AUX->power well 3 dependency
    
    v4:
    - Rebase
    
    v5:
    - Detach AUX power wells from the INIT power domain. These power wells
      can only be enabled in a TC/TBT connected state and otherwise not
      needed during driver initialization.
    
    v6:
    - Use _MMIO_PORT(...) instead _MMIO(_PICK(...)) (Paulo)
      Fix checkpatch warnings.
    
    Cc: Animesh Manna <animesh.manna@intel.com>
    Cc: Rakshmi Bhatia <rakshmi.bhatia@intel.com>
    Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
    Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
    Reviewed-by: Animesh Manna <animesh.manna@intel.com> (v1)
    Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20180626142232.22361-1-imre.deak@intel.com
    67ca07e7
intel_display.h 10.2 KB