• Shanker Donthineni's avatar
    arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC · 6ae4b6e0
    Shanker Donthineni authored
    The DCache clean & ICache invalidation requirements for instructions
    to be data coherence are discoverable through new fields in CTR_EL0.
    The following two control bits DIC and IDC were defined for this
    purpose. No need to perform point of unification cache maintenance
    operations from software on systems where CPU caches are transparent.
    
    This patch optimize the three functions __flush_cache_user_range(),
    clean_dcache_area_pou() and invalidate_icache_range() if the hardware
    reports CTR_EL0.IDC and/or CTR_EL0.IDC. Basically it skips the two
    instructions 'DC CVAU' and 'IC IVAU', and the associated loop logic
    in order to avoid the unnecessary overhead.
    
    CTR_EL0.DIC: Instruction cache invalidation requirements for
     instruction to data coherence. The meaning of this bit[29].
      0: Instruction cache invalidation to the point of unification
         is required for instruction to data coherence.
      1: Instruction cache cleaning to the point of unification is
          not required for instruction to data coherence.
    
    CTR_EL0.IDC: Data cache clean requirements for instruction to data
     coherence. The meaning of this bit[28].
      0: Data cache clean to the point of unification is required for
         instruction to data coherence, unless CLIDR_EL1.LoC == 0b000
         or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000).
      1: Data cache clean to the point of unification is not required
         for instruction to data coherence.
    Co-authored-by: default avatarPhilip Elcan <pelcan@codeaurora.org>
    Reviewed-by: default avatarMark Rutland <mark.rutland@arm.com>
    Signed-off-by: default avatarShanker Donthineni <shankerd@codeaurora.org>
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    6ae4b6e0
cacheflush.h 5.18 KB