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Felipe Balbi authored
Say we have three requests prepared to the HW (reqA, reqB, and reqC). All of them are composed of SG-lists with several entries and they all requests interrupt only on last TRBs of the SG-list. When we get interrupt for reqA, it could be that reqB is already half-way transferred and some of its TRBs will have HWO already cleared. It's okay to free up TRBs without HWO bit set, but we need to guarantee we don't giveback a request that's half-way transferred as that will confuse gadget drivers. Signed-off-by:
Felipe Balbi <felipe.balbi@linux.intel.com>
7282c4ef