• Felipe Balbi's avatar
    mfd: tps65218: Make INT[12] and STATUS registers volatile · 773328da
    Felipe Balbi authored
    STATUS register can be modified by the HW, so we
    should bypass cache because of that.
    
    In the case of INT[12] registers, they are the ones
    that actually clear the IRQ source at the time they
    are read. If we rely on the cache for them, we will
    never be able to clear the interrupt, which will cause
    our IRQ line to be disabled due to IRQ throttling.
    
    Fixes: 44b4dc61 mfd: tps65218: Add driver for the TPS65218 PMIC
    Cc: <stable@vger.kernel.org> # v3.15+
    Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
    Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
    773328da
tps65218.c 6.83 KB