• Ido Shamay's avatar
    net/mlx4_core: Enable CQE/EQE stride support · 77507aa2
    Ido Shamay authored
    This feature is intended for archs having cache line larger then 64B.
    
    Since our CQE/EQEs are generally 64B in those systems, HW will write
    twice to the same cache line consecutively, causing pipe locks due to
    he hazard prevention mechanism. For elements in a cyclic buffer, writes
    are consecutive, so entries smaller than a cache line should be
    avoided, especially if they are written at a high rate.
    
    Reduce consecutive writes to same cache line in CQs/EQs, by allowing the
    driver to increase the distance between entries so that each will reside
    in a different cache line. Until the introduction of this feature, there
    were two types of CQE/EQE:
    
    1. 32B stride and context in the [0-31] segment
    2. 64B stride and context in the [32-63] segment
    
    This feature introduces two additional types:
    
    3. 128B stride and context in the [0-31] segment (128B cache line)
    4. 256B stride and context in the [0-31] segment (256B cache line)
    
    Modify the mlx4_core driver to query the device for the CQE/EQE cache
    line stride capability and to enable that capability when the host
    cache line size is larger than 64 bytes (supported cache lines are
    128B and 256B).
    
    The mlx4 IB driver and libmlx4 need not be aware of this change. The PF
    context behaviour is changed to require this change in VF drivers
    running on such archs.
    Signed-off-by: default avatarIdo Shamay <idos@mellanox.com>
    Signed-off-by: default avatarJack Morgenstein <jackm@dev.mellanox.co.il>
    Signed-off-by: default avatarOr Gerlitz <ogerlitz@mellanox.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    77507aa2
fw.h 6.15 KB