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Yakir Yang authored
Both hsync/vsync polarity and interlace mode can be parsed from drm display mode, and dynamic_range and ycbcr_coeff can be judge by the video code. But presumably Exynos still relies on the DT properties, so take good use of mode_fixup() in to achieve the compatibility hacks. Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by:
Caesar Wang <wxt@rock-chips.com> Tested-by:
Douglas Anderson <dianders@chromium.org> Tested-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by:
Yakir Yang <ykk@rock-chips.com>
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