• Jon Hunter's avatar
    ARM: tegra: Ensure entire dcache is flushed on entering LP0/1 · 5883ac20
    Jon Hunter authored
    Tegra support several low-power (LPx) states, which are:
    - LP0: CPU + Core voltage off and DRAM in self-refresh
    - LP1: CPU voltage off and DRAM in self-refresh
    - LP2: CPU voltage off
    
    When entering any of the above states the tegra_disable_clean_inv_dcache()
    function is called to flush the dcache. The function
    tegra_disable_clean_inv_dcache() will either flush the entire data cache or
    up to the Level of Unification Inner Shareable (LoUIS) depending on the
    value in r0. When tegra_disable_clean_inv_dcache() is called by
    tegra20_sleep_core_finish() or tegra30_sleep_core_finish(), to enter LP0
    and LP1 power state, the r0 register contains a physical memory address
    which will not be equal to TEGRA_FLUSH_CACHE_ALL (1) and so the data cache
    will be only flushed to the LoUIS. However, when
    tegra_disable_clean_inv_dcache() called by tegra_sleep_cpu_finish() to
    enter to LP2 power state, r0 is set to TEGRA_FLUSH_CACHE_ALL to flush the
    entire dcache.
    
    Please note that tegra20_sleep_core_finish(), tegra30_sleep_core_finish()
    and tegra_sleep_cpu_finish() are called by the boot CPU once all other CPUs
    have been disabled and so it seems appropriate to flush the entire cache at
    this stage.
    
    Therefore, ensure that r0 is set to TEGRA_FLUSH_CACHE_ALL when calling
    tegra_disable_clean_inv_dcache() from tegra20_sleep_core_finish() and
    tegra30_sleep_core_finish().
    Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
    Reviewed-by: default avatarJoseph Lo <josephl@nvidia.com>
    Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
    5883ac20
sleep-tegra20.S 13.9 KB