OMAP2420 and OMAP2430 chips each have two on-chip APLLs.  When locked,
one APLL generates a 96 MHz rate; the other, a 54 MHz rate.
Previously we treated these clocks as fixed-rate clocks at the locked
rates, but this isn't quite right.  The locked rate should be returned
when the APLL is locked, and a zero rate should be returned when the
APLL is stopped.  This patch adds the infrastructure that will be used
by the CCF changes.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>