• David S. Miller's avatar
    sparc64: Fix MSIQ HV call ordering in pci_sun4v_msiq_build_irq(). · 7cc85833
    David S. Miller authored
    This silently was working for many years and stopped working on
    Niagara-T3 machines.
    
    We need to set the MSIQ to VALID before we can set it's state to IDLE.
    
    On Niagara-T3, setting the state to IDLE first was causing HV_EINVAL
    errors.  The hypervisor documentation says, rather ambiguously, that
    the MSIQ must be "initialized" before one can set the state.
    
    I previously understood this to mean merely that a successful setconf()
    operation has been performed on the MSIQ, which we have done at this
    point.  But it seems to also mean that it has been set VALID too.
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    7cc85833
pci_sun4v.c 23.7 KB