• Catalin Marinas's avatar
    arm64: MMU definitions · 4f04d8f0
    Catalin Marinas authored
    The virtual memory layout is described in
    Documentation/arm64/memory.txt. This patch adds the MMU definitions for
    the 4KB and 64KB translation table configurations. The SECTION_SIZE is
    2MB with 4KB page and 512MB with 64KB page configuration.
    
    PHYS_OFFSET is calculated at run-time and stored in a variable (no
    run-time code patching at this stage).
    
    On the current implementation, both user and kernel address spaces are
    512G (39-bit) each with a maximum of 256G for the RAM linear mapping.
    Linux uses 3 levels of translation tables with the 4K page configuration
    and 2 levels with the 64K configuration. Extending the memory space
    beyond 39-bit with the 4K pages or 42-bit with 64K pages requires an
    additional level of translation tables.
    
    The SPARSEMEM configuration is global to all AArch64 platforms and
    allows for 1GB sections with SPARSEMEM_VMEMMAP enabled by default.
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    Acked-by: default avatarTony Lindgren <tony@atomide.com>
    Acked-by: default avatarNicolas Pitre <nico@linaro.org>
    Acked-by: default avatarOlof Johansson <olof@lixom.net>
    Acked-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
    Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
    4f04d8f0
pgtable-hwdef.h 3.06 KB