• Serge Semin's avatar
    mips: Add CP0 Write Merge config support · 742318ad
    Serge Semin authored
    CP0 config register may indicate whether write-through merging
    is allowed. Currently there are two types of the merging available:
    SysAD Valid and Full modes. Whether each of them are supported by
    the core is implementation dependent. Moreover whether the ability
    to change the mode also depends on the chip family instance. Taking
    into account all of this we created a dedicated mm_config() method
    to detect and enable merging if it's supported. It is called for
    MIPS-type processors at CPU-probe stage and attempts to detect whether
    the write merging is available. If it's known to be supported and
    switchable, then switch on the full mode. Otherwise just perform the
    CP0.Config.MM field analysis.
    
    In addition there are platforms like InterAptiv/ProAptiv, which do have
    the MM bit field set by default, but having write-through cacheing
    unsupported makes write-merging also unsupported. In this case we just
    ignore the MM field value.
    Co-developed-by: default avatarAlexey Malahov <Alexey.Malahov@baikalelectronics.ru>
    Signed-off-by: default avatarAlexey Malahov <Alexey.Malahov@baikalelectronics.ru>
    Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
    Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
    Cc: Paul Burton <paulburton@kernel.org>
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: Arnd Bergmann <arnd@arndb.de>
    Cc: Rob Herring <robh+dt@kernel.org>
    Cc: devicetree@vger.kernel.org
    Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
    742318ad
cpu.h 16.3 KB