• Serge Semin's avatar
    mips: MAAR: Add XPA mode support · 9ee195fd
    Serge Semin authored
    When XPA mode is enabled the normally 32-bits MAAR pair registers
    are extended to be of 64-bits width as in pure 64-bits MIPS
    architecture. In this case the MAAR registers can enable the
    speculative loads/stores for addresses of up to 39-bits width.
    But in this case the process of the MAAR initialization changes a bit.
    The upper 32-bits of the registers are supposed to be accessed by mean
    of the dedicated instructions mfhc0/mthc0 and there is a CP0.MAAR.VH
    bit which should be set together with CP0.MAAR.VL as indication
    of the boundary validity. All of these peculiarities were taken into
    account in this commit so the speculative loads/stores would work
    when XPA mode is enabled.
    Co-developed-by: default avatarAlexey Malahov <Alexey.Malahov@baikalelectronics.ru>
    Signed-off-by: default avatarAlexey Malahov <Alexey.Malahov@baikalelectronics.ru>
    Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
    Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
    Cc: Paul Burton <paulburton@kernel.org>
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: Arnd Bergmann <arnd@arndb.de>
    Cc: Rob Herring <robh+dt@kernel.org>
    Cc: linux-pm@vger.kernel.org
    Cc: devicetree@vger.kernel.org
    Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
    9ee195fd
init.c 14.6 KB