• Sergei Shtylyov's avatar
    [PATCH] ide: HPT3xxN clocking fixes · 836c0063
    Sergei Shtylyov authored
    Fix serious problems with the HPT372N clock turnaround code:
    
    - the wrong ports were written to when called for the secondary channel;
    
    - it didn't serialize access to the channels;
    
    - turnaround shou;dn't be done on 66 MHz PCI;
    
    - caching the clock mode per-channel caused it to get out of sync with the
      actual register value.
    
    Additionally, avoid calibrating PLL twice (for each channel) as the second try
    results in a wrong PCI frequency and thus in the wrong timings.
    
    Make the driver deal with HPT302N and HPT371N correctly -- the clocking and
    (seemingly) a need for clock tunaround is the same as for HPT372N.  HPT371/N
    chips have only one, secondary channel, so avoid touching their "pure virtual"
    primary channel, and disable it if the BIOS haven't done this already.
    
    Also, while at it, disable UltraATA/133 for HPT372 by default -- 50 MHz DPLL
    clock don't allow for this speed anyway.  And remove the traces of the former
    bad patch that wasn't even applicable to this version of driver.
    
    Has been tested on HPT370/371N, unfortunately I don't have an instant access
    to the other chips...
    Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
    Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
    Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
    Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
    Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
    836c0063
hpt366.c 49.1 KB