• Dan Williams's avatar
    libnvdimm, nfit: fix persistence domain reporting · fe9a552e
    Dan Williams authored
    The persistence domain is a point in the platform where once writes
    reach that destination the platform claims it will make them persistent
    relative to power loss. In the ACPI NFIT this is currently communicated
    as 2 bits in the "NFIT - Platform Capabilities Structure". The bits
    comprise a hierarchy, i.e. bit0 "CPU Cache Flush to NVDIMM Durability on
    Power Loss Capable" implies bit1 "Memory Controller Flush to NVDIMM
    Durability on Power Loss Capable".
    
    Commit 96c3a239 "libnvdimm: expose platform persistence attr..."
    shows the persistence domain as flags, but it's really an enumerated
    hierarchy.
    
    Fix this newly introduced user ABI to show the closest available
    persistence domain before userspace develops dependencies on seeing, or
    needing to develop code to tolerate, the raw NFIT flags communicated
    through the libnvdimm-generic region attribute.
    
    Fixes: 96c3a239 ("libnvdimm: expose platform persistence attr...")
    Reviewed-by: default avatarDave Jiang <dave.jiang@intel.com>
    Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
    Cc: Ross Zwisler <ross.zwisler@linux.intel.com>
    Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
    fe9a552e
region_devs.c 29 KB