• Catalin Marinas's avatar
    ARM: LPAE: MMU setup for the 3-level page table format · 1b6ba46b
    Catalin Marinas authored
    This patch adds the MMU initialisation for the LPAE page table format.
    The swapper_pg_dir size with LPAE is 5 rather than 4 pages. A new
    proc-v7-3level.S file contains the TTB initialisation, context switch
    and PTE setting code with the LPAE. The TTBRx split is based on the
    PAGE_OFFSET with TTBR1 used for the kernel mappings. The 36-bit mappings
    (supersections) and a few other memory types in mmu.c are conditionally
    compiled.
    Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    1b6ba46b
proc-v7-3level.S 4.44 KB