• Ke Wei's avatar
    [ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define · 1219715d
    Ke Wei authored
    Some Feroceon-based SoCs have an MBUS bridge interrupt controller
    that requires writing a one instead of a zero to clear edge
    interrupt sources such as timer expiry.
    
    This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform
    code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or
    BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform.
    Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
    1219715d
orion5x.h 6.43 KB