• Rhyland Klein's avatar
    clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate · 86c679a5
    Rhyland Klein authored
    This removes the conversion from pdiv to hw, which is already taken
    care of by _get_table_rate before this code is run. This avoids
    incorrectly converting pdiv to hw twice and getting the wrong hw value.
    
    Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while
    setting all the other fields.
    
    In order to prevent regressions on earlier SoC generations, all of the
    frequency tables need to be updated so that they contain the actual
    divider values. If they contain hardware values these would be converted
    to hardware values again, yielding the wrong value.
    Signed-off-by: default avatarRhyland Klein <rklein@nvidia.com>
    [treding@nvidia.com: fix regressions on earlier SoC generations]
    Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
    86c679a5
clk-tegra30.c 55.3 KB