• Jordan Crouse's avatar
    drm/msm: Ensure that the hardware write pointer is valid · 88b333b0
    Jordan Crouse authored
    Currently the value written to CP_RB_WPTR is calculated on the fly as
    (rb->next - rb->start). But as the code is designed rb->next is wrapped
    before writing the commands so if a series of commands happened to
    fit perfectly in the ringbuffer, rb->next would end up being equal to
    rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR.
    
    The easiest way to fix this is to mask WPTR when writing it to the
    hardware; it makes the hardware happy and the rest of the ringbuffer
    math appears to work and there isn't any point in upsetting anything.
    Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
    [squash in is_power_of_2() check]
    Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
    88b333b0
adreno_gpu.c 12.1 KB